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3D7502
MONOLITHIC MANCHESTER DECODER (SERIES 3D7502)
FEATURES
* * * * * * * All-silicon, low-power CMOS technology TTL/CMOS compatible inputs and outputs Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) Low ground bounce noise Maximum data rate: 50 MBaud Data rate range: 15%
data 3 (R) delay devices, inc.
PACKAGES
RX N/C N/C 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD N/C N/C N/C N/C N/C DATB
RX CLK N/C GND
1 2 3 4
8 7 6 5
VDD N/C N/C DATB
CLK N/C N/C GND
3D7502M-xxx DIP (.300) 3D7502H-xxx Gull Wing (.300) 3D7502Z-xxx SOIC (.150)
3D7502-xxx DIP (.300) 3D7502G-xxx Gull Wing (.300) 3D7502D-xxx SOIC (.150)
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D7502 product family consists of monolithic CMOS Manchester RX Signal Input Decoders. The unit accepts at the RX input a bi-phase-level, CLK Signal Output (Clock) embedded-clock signal. In this encoding mode, a logic one is DATB Signal Output (Data) represented by a high-to-low transition within the bit cell, while a logic VCC +5 Volts zero is represented by a low-to-high transition. The recovered clock GND Ground and data signals are presented on CLK and DATB, respectively, with the data signal inverted. The operating baud rate (in MBaud) is specified by the dash number. The input baud rate may vary by as much as 15% from the nominal device baud rate without compromising the integrity of the information received. Because the 3D7502 is not PLL-based, it does not require a long preamble in order to lock onto the received signal. Rather, the device requires at most one bit cell before the data presented at the output is valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise turned off. The all-CMOS 3D7502 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL Manchester Decoders. It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads. It is offered in standard 8-pin and 14-pin auto-insertable DIPs and space saving surface mount 8-pin and 14pin SOICs.
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
3D7502-5 3D7502-10 3D7502-20 3D7502-25 3D7502-30 3D7502-40 3D7502-50
BAUD RATE (MBaud) Nominal Minimum Maximum
5.00 10.00 20.00 25.00 30.00 40.00 50.00 4.25 8.50 17.00 21.25 25.50 34.00 42.50 5.75 11.50 23.00 28.75 34.50 46.00 57.50 (c)1997 Data Delay Devices
NOTES: Any baud rate between 5 and 50 MBaud not shown is also available at no extra cost.
Doc #97032
5/19/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D7502
APPLICATION NOTES
The 3D7502 Manchester Decoder samples the input at precise pre-selected intervals to retrieve the data and to recover the clock from the received data stream. Its architecture comprises finely tuned delay elements and proprietary circuitry which, in conjunction with other circuits, implement the data decoding and clock recovery function.
OUTPUT SIGNAL CHARACTERISTICS
The 3D7502 presents at its outputs the decoded data (inverted) and the recovered clock. The decoded data is valid at the rising edge of the clock. The clock recovery function operates in two modes dictated by the input data stream bit sequence. When a data bit is succeeded by its inverse, the clock recovery circuit is engaged and forces the clock output low for a time equal to one over twice the baud rate. Otherwise, the input is presented at the clock output unchanged, shifted in time. When engaged, the clock recovery circuit generates a low-going pulse of fixed width. Therefore, the clock duty cycle is strongly dependent on the baud rate, as this will affect the clock-high duration. The clock output falling edge is not operated on by the clock recovery circuitry. It, therefore, preserves more accurately the clock frequency information embedded in the transmitted data. Therefore, it can be used, if it is desired, to retrieve clock frequency information.
INPUT SIGNAL CHARACTERISTICS
Encoded data transmitted from a source arrives at its destination corrupted. Such corruption of the received data manifests itself as jitter and/or pulse width distortion at the input to the device. The instantaneous deviations from nominal Baud Rate and/or Pulse Width (high or low) adversely impact the data extraction and clock recovery function if their published limits are exceeded. See Table 4, Allowed Baud Rate/Duty Cycle. The 3D7502 Manchester Decoder Data Input is TTL compatible. The user should assure himself that the 1.5 volt TTL threshold is used when referring to all timing, especially the input pulse widths.
FREQUENCY (JITTER) ERRORS
The 3D7502 Manchester Decoder, being a selftimed device, is tolerant of frequency modulation (jitter) present in the input data stream, provided that the input data pulse width variations remain within the allowable ranges.
POWER SUPPLY AND TEMPERATURE CONSIDERATIONS
CMOS integrated circuitry is strongly dependent on power supply and temperature. The monolithic 3D7502 Manchester Decoder utilizes novel and innovative compensation circuitry to minimize timing variations induced by fluctuations in power supply and/or temperature. 1 0 0 1
ENCODED RECEIVED (RX)
0
1
0
1
tC tCL
CLOCK (CLK) DATA (DATB) DECODED
tCWL
tCD
1
0
1
1
0
0
1
Figure 1: Timing Diagram
Doc #97032
5/19/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
3D7502
.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN -0.3 -0.3 -10 -55 MAX 7.0 VDD+0.3 10 150 300 UNITS V V mA C C NOTES
25C 10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current Output Rise & Fall Time SYMBOL IDD VIH VIL IIH IIL IOH IOL T R & TF MIN 2.0 0.8 1.0 1.0 -4.0 4.0 2 MAX 40 UNITS mA V V A A mA mA ns NOTES
VIH = VDD VIL = 0V VDD = 4.75V VOH = 2.4V VDD = 4.75V VOL = 0.4V CLD = 5 pf
*IDD(Dynamic) = 2 * CLD * VDD * F where: CLD = Average capacitance load/pin (pf) F = Input frequency (GHz)
Input Capacitance = 10 pf typical Output Load Capacitance (CLD) = 25 pf max
TABLE 4: AC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V, except as noted) PARAMETER Nominal Input Baud Rate Allowed Input Baud Rate Deviation Allowed Input Baud Rate Deviation Allowed Input Baud Rate Deviation Allowed Input Duty Cycle Bit Cell Time Input Data Edge to Clock Falling Edge Clock Width Low Clock Falling Edge to Data Transition
SYMBOL
f BN fB fB fB
MIN 5 -0.15 f BN -0.05 f BN -0.03 f BN 42.5
TYP
MAX 50 0.15 f BN 0.05 f BN 0.03 f BN
UNITS MBaud MBaud MBaud MBaud % ns ns ns ns
NOTES 25C, 5.00V -40C to 85C 4.75V to 5.25V -55C to 125C 4.75V to 5.25V
tc tCL tCWL tCD 3.0
50.0 1000/fB 0.75 tc 500/fBN 4.0
57.5
2ns or 5%
5.0
Doc #97032
5/19/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3D7502
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC 3oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High = 3.0V 0.1V Low = 0.0V 0.1V Source Impedance: 50 Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 1/(2*BAUD) Period: PERIN = 1/BAUD OUTPUT: Rload: Cload: Threshold: 10K 10% 5pf 10% 1.5V (Rising & Falling)
Device Under Test
10K
Digital Scope 5pf
470
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
COMPUTER SYSTEM
PRINTER
WAVEFORM GENERATOR
OUT TRIG
IN
DEVICE UNDER TEST (DUT)
OUT
IN TRIG
DIGITAL SCOPE
Figure 2: Test Setup
PERIN PWIN tRISE INPUT SIGNAL
2.4V 1.5V 0.6V
tFALL VIH
2.4V 1.5V 0.6V
VIL tPHL
tPLH OUTPUT SIGNAL VOH
1.5V
1.5V
VOL
Figure 3: Timing Diagram
Doc #97032
5/19/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4

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